1. Field of the Invention
The present invention relates to an interrupt control device for use with an information processing device, along with methods for controlling such an interrupt control device and program products for executing such methods. In particular, the present invention relates to such devices, methods and program products for optimizing the timing of interrupts to a central processing unit of the information processing device.
2. Background
When an input/output (I/O) device or sub-CPU (Central Processing Unit) operates together with a main CPU to perform data processing operations or control, the input/output device or sub-CPU typically issues an interrupt to the main CPU to operate in synchronization with the main CPU (see, for example, Published Unexamined Patent Application No. JP10-275136).
Using such a methodology, it can take an ISR (Interrupt Service Routine) considerable time to start up and operate after an OS (Operating System) running on the CPU receives an interrupt, resulting in performance degradation due to delays in data transfer or synchronization between the main CPU and an input/output device or a sub-CPU.
One approach to avoiding such delay is to poll I/O devices and sub-CPUs from the main CPU to monitor them, instead of waiting for interrupts. However, it is difficult for the main CPU to efficiently perform other jobs during polling, causing other, polling-related delays and further performance degradation.
Therefore, an object of the present invention is to provide an information processing device, an interrupt control device and method, and a program product for implementing such methods, to address the stated shortcomings of the prior art. This object is achieved by the combination of features set forth in the independent claims appended hereto. Other, specific and alternate embodiments of the present invention are set out in the dependent claims, also appended hereto.